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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Six Output Ranges: 2000 MHz to 2550 MHz 1700 MHz to 2150 MHz 1600 MHz to 1950 MHz 1400 MHz to 1800 MHz 1150 MHz to 1400 MHz 1000 MHz to 1250 MHz External L for Lower Frequencies
Integrated Synthesizer and VCO ADF4360
GENERAL DESCRIPTION
Divide-by-2 output +2.7 V to +3.3V Power Supply 1.8 V Logic Compatibility Integer-N Synthesizer Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33 Programmable Output Power Level Programmable Core Power Level 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power Down Mode APPLICATIONS Wireless Handsets (DECT, GSM, PCS, DCS, WCDMA) Test Equipment Wireless LANS CATV Equipment
The ADF4360 family is a fully integrated integer-N synthesizer and voltage controlled oscillator (VCO). The user has the choice of seven output frequency ranges; the ADF4360-1 is designed for a center frequency of 2400MHz, the ADF4360-2 for 2000MHz, the ADF43603 for 1800 MHz, the ADF4360-4 for 1600MHz, the ADF4360-5 for 1300MHz and the ADF4360-6 for 1150 MHz. The ADF4360-7 center frequency is set by external inductors. In addition, there is a divide-by-2 option available, whereby the user gets an RF output center frequency of either 1200MHz (ADF4360-1), 1000MHz (ADF4360-2), 900 MHz (ADF4360-3) etc. Control of all the on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7V to 3.3V and can be powered down when not in use.
ADF4360-1/2/3/4/5/6 FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD CE RSET
ADF4360-1/2/3/4/5/6
MULTIPLEXER
MUXOUT
REFIN
14-BIT R COUNTER
LOCK DETECT
CLK DATA LE
PHASE COMPARATOR
24-BIT DATA REGISTER
24-BIT FUNCTION LATCH
CHARGE PUMP
CP
VVCO VTUNE CC CN
INTEGER REGISTER
13-BIT B COUNTER
VCO CORE
OUTPUT STAGE
RFOUT A RFOUT B
+ -
PRESCALER P/P+1
LOAD LOAD
6-BIT A COUNTER
MULTIPLEXER
N = (BP + A)
/2
AGND
DGND
CPGND
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REV. PrP 01/03
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
ADF4360-SPECIFICATIONS1
Parameter REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity3 0 to VDD max REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency4 CHARGE PUMP ICP sink/source 5 High Value Low Value R SET Range ICP 3-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature RF OUTPUT CHARACTERISTICS VCO Output Frequency ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-7 VCO Sensitivity ADF4360-1/2 ADF4360-3/4 ADF4360-5/6 Frequency Pushing Frequency Pulling Harmonic Content VCO Output Power Range VCO Tuning Range LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES A VDD D V DD IDD6 (AIDD + DIDD ) I VCO I RFOUT Low Power Sleep Mode B Version 10/100 -5/0 10 100 1
(AVDD = DVDD = VVCO = +3V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
B Chips2 (Typical) 10/100 -5/0 10 100 1 Units Test Conditions/Comments
MHz min/max dBm min/max pF max A max MHz max
For f < 10MHz, use dc-coupled CMOS compatible square wave AC coupled. (CMOS compatible)
With RSET = 4.7k 2.5 0.312 2.7/10 1 2 1.5 2 2.5 0.312 2.7/10 1 2 1.5 2 mA typ mA typ k typ nA typ % typ % typ % typ
0.5V VCP 0.5V VCP VCP = VP/2
VP - 0.5 VP - 0.5
2000/2550 1700/2150 1600/1950 1400/1800 1150/1400 1000/1250 TBD 60 50 40 4 200 -10 -12/-3 1.5/2.5 1.35 0.6 1 10 DV DD -0.4 DV DD -0.4 500 0.4 2.7/3.3 A VDD 9.0 10-28 3.5-11.0 5
2000/2550 1700/2150 1600/1950 1400/1800 1150/1400 1000/1250 TBD 60 50 40 4 200 -10 -12/-3 1.5/2.5 1.35 0.6 1 10 V DD -0.4 V DD -0.4 500 0.4 2.7/3.3 A VDD 9.0 10.0-28.0 3.5-11.0 5
MHz MHz MHz MHz MHz MHz MHz
min/max min/max min/max min/max min/max min/max min/max
Center Center Center Center Center Center
Frequency: Frequency: Frequency: Frequency: Frequency: Frequency:
2250MHz 2000MHz 1800MHz 1600MHz 1300MHz 1150MHz
MHz/Volt typ
Fundamental Frequency Selected 30/25/20 with Divide by two selected
MHz/Volt typ kHz typ dBc typ dBm min/max V min/max V min V max A max pF max V min V min A max V max V min/V max mA mA mA A typ
Into 2.00 VSWR Load
Programmable in 3dB steps.Table X
Open drain output chosen. pull-up to 1.8V CMOS output chosen IOL = 500A
1k
VCO core power level is programmable; as is the RF Output Stage
NOTES 1. Operating temperature range is as follows: B Version: -40C to +85C. 2. Only the ADF4360-7 is offered in die (chip) form. The B Chip specifications are given as typical values. 3. AVDD = DVDD = VVCO = 3V 4. Guaranteed by design. Sample tested to ensure compliance. 5. ICP is internally modified to maintain constant loop gain over the frequency range -2- 6. TA = +25C; AV DD = DVDD = V VCO = 3V; P = 16
REV. PrP 01/03
PRELIMINARY TECHNICAL DATA
ADF4360 -SPECIFICATIONS1
Parameter NOISE CHARACTERISTICS
Synthesizer Phase Noise Floor 2 VCO Phase Noise Performance Output Phase Noise Performance3 2250 MHz output4 2000 MHz output5 1800 MHz output6 1600 MHz output7 1300 MHz output8 1150 MHz output9 Spurious Signals 2250MHz output 4 2000MHz output 5 1800MHz output 6 1600MHz output 7 1300MHz output 8 1150 MHz output9 -171 -164 -130 -141 -80 -83 -84 -84 -85 -85 -70/-72 -70/-72 -70/-72 -70/-72 -70/-72 -70/-72 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc dBc dBc dBc dBc typ typ typ typ typ typ typ typ typ typ typ typ typ typ typ typ
(AVDD = DVDD = VVCO = +3V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
B
Units
Test Conditions/Comments
@ 25kHz PFD Frequency @ 200kHz PFD Frequency @ 800kHz offset from carrier @ 3MHz Offset from carrier @ VCO Output ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6
NOTES 1. Operating temperature range is as follows: B Version: -40C to +85C. 2. The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 3. The phase noise is measured with the EVAL-ADF4360EBX Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10MHz @ 0dBm). 4. f REFIN = 10 MHz; f PFD = 200 kHz; Offset frequency = 1 kHz; N = 11250; Loop B/W = 10kHz 5. f REFIN = 10 MHz; f PFD = 200kHz; Offset frequency = 1 kHz; N = 10000; Loop B/W = 10kHz 6. f REFIN = 10 MHz; f PFD = 200kHz; Offset frequency = 1 kHz; N = 9000; Loop B/W = 10kHz 7. f REFIN = 10 MHz; f PFD = 200kHz; Offset frequency = 1 kHz; N = 8000; Loop B/W = 10kHz 8. f REFIN = 10 MHz; f PFD = 200kHz; Offset frequency = 1 kHz; N = 6500; Loop B/W = 10kHz 9. f REFIN = 10 MHz; f PFD = 200kHz; Offset frequency = 1 kHz; N = 5750; Loop B/W = 10kHz
ORDERING GUIDE
Model ADF4360-1BCP ADF4360-2BCP ADF4360-3BCP ADF4360-4BCP ADF4360-5BCP ADF4360-6BCP ADF4360-7BCP
*
Temperature Range -40C -40C -40C -40C -40C -40C -40C to to to to to to to +85C +85C +85C +85C +85C +85C +85C
Frequency Range 2000-2550 MHz 1700-2150 MHz 1600-1950 MHz 1400-1800 MHz 1150-1400 MHz 1000-1250 MHz Set By External L
Package Option* CP-24 CP-24 CP-24 CP-24 CP-24 CP-24 CP-24
CP = Chip Scale Package Contact the factory for chip availability
PIN CONFIGURATION TOP VIEW
MUXOUT 20 AGND DVDD CP CE LE 19
24
22
CPGND AVDD AGND RFOUTA RFOUTB V VCO
1 2 3 4 5 6
PIN 1 IDENTIFIER
23
21
18
17
DATA CLK REFIN D GND CN RSET
ADF4360 TOP VIEW
16 15
14
13
AGND 10
AGND / L 11 2
V TUNE
AGND / L 1
AGND
CC 12
7
8
9
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REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
TIMING CHARACTERISTICS
Parameter t1 t2 t3 t4 t5 t6 Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20
(AVDD = DVDD = VVCO = +3V 10%; AGND = DGND = 0 V; 1.8V and 3V Logic Levels Used; TA = TMIN to TMAX unless otherwise noted)
Units ns ns ns ns ns ns min min min min min min
Test Conditions/Comments DATA to CLOCK Set Up Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Set Up Time LE Pulse Width
NOTE Guaranteed by Design but not Production Tested.
t3 t4
CLOCK
t1 t2 DB0 (LSB)
(CONTROL BIT C1)
DATA
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
t6
LE
t5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS1,
2
(TA = +25C unless otherwise noted) AVDD to GND3 ..................................-0.3 V to +3.6 V AVDD to DV DD .....................................-0.3 V to +0.3 V VP to GND.........................................-0.3 V to +3.6 V VVCO to GND......................................-0.3 V to +3.6 V VVCO to AVDD ......................................-0.3 V to +0.3 V Digital I/O Voltage to GND..........-0.3 V to VDD + 0.3 V Analog I/O Voltage to GND..........-0.3 V to VDD + 0.3 V REFIN, to GND............................-0.3 V to VDD + 0.3 V OperatingTemperature Range Industrial (B Version).........................-40C to +85C Maximum Junction Temperature........................+150C
CSP JA Thermal Impedance (Paddle Soldered).......................................50C/W (Paddle Not Soldered).................................88C/W Lead Temperature, Soldering Vapor Phase (60 sec)......................................+215C Infrared (15 sec)............................................+220C
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high-performance RF integrated circuit with an ESD rating of < 2kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3. GND = AGND = DGND = 0V
TRANSISTOR COUNT
TBA (CMOS) and TBA (Bipolar)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4360 family features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICEI
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PRELIMINARY TECHNICAL DATA ADF4360
PIN DESCRIPTION
Mnemonic A VDD D V DD R SET
Function Analog Power Supply. This may range from 2.7V to 3.3V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Digital Power Supply. This may range from 2.7V to 3.3V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer. The nominal voltage potential at the RSET pin is 0.6V. The relationship between ICP and RSET is
ICPmax =
11.75 RSET
MUXOUT CP V VCO V TUNE L1 L2 CC CN RF OUT A RF O U T B CPGND DGND AGND LE DATA CLK
So, with RSET = 4.7k, ICPmax = 2.5mA. This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be accessed externally. Charge Pump Output. When enabled this provides ICP to the external loop filter, which in turn drives the internal VCO. Power supply for the VCO. This may range from 2.7V to 3.3V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VVCO must be the same value as AVDD. Control input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT voltage. ADF4360-7 only. An external inductor should be connected to this pin to set the ADF4360-7 output frequency. ADF4360-7 only. An external inductor should be connected to this pin to set the ADF4360-7 output frequency. Internal compensation node. This pin must be decoupled to ground with a 10nF capacitor. Internal compensation node. This pin must be decoupled to VVCO with a 10uF capacitor. VCO output. The output level is programmable from -3dBm to -12dBm. VCO complementary output. The output level is programmable from -3dBm to -12dBm. Charge Pump Ground. This is the ground return path for the charge pump. Digital Ground. Analog Ground. This is the ground return path of the prescaler & VCO. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three state mode. Taking the pin high will power up the device depending on the status of the power-down bits. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100k. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled.
CE REFIN
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PRELIMINARY TECHNICAL DATA ADF4360 Typical Performance Characteristics
ATTEN RL 0dBm
10dB
VAVG 10dB/
19
MKR 1.000kHz
-93.36dB/Hz
D
CENTER *RBW 10Hz
1.900000000GHz VBW 10Hz
SPAN SWP
5.000kHz 1.91sec
TPC 1. VCO Phase Noise (Unlocked)
TPC 3. Close-In Phase Noise at 1900MHz (1.25MHz Channel Spacing)
ATTEN RL 0dBm 10dB VAVG 10dB/ 100 MKR 1.270MHz -73.83dB
D
CENTER *RBW 10kHz
1.900025GHz VBW 10kHz
SPAN SWP
3.000MHz 75.0ms
TPC 2. VCO Phase Noise (Locked)
TPC 4. Reference Spurs at 1900MHz (1.25MHz Channel Spacing)
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REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The Reference Input stage is shown below in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normallyopen. When Powerdown is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on powerdown.
A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300MHz or less. Thus, with an VCO frequency of 2.5GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. Pulse Swallow Function The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R . The equation for the VCO frequency is as follows:
Powerdown Control
NC
100k To R Counter Buffer
fVCO = [(P x B) + A] x fREFIN/R f VCO P B A Ouput Frequency of voltage controlled oscillator (VCO). Preset modulus of dual modulus prescaler (8/9, 16/17, etc.,). Preset Divide Ratio of binary 13-bit counter (3 to 8191). Preset Divide Ratio of binary 6-bit swallow counter (0 to 31).
SW2
REFIN
NC
SW1 SW3
NO
Figure 2. Reference Input Stage
PRESCALER (P/P+1) The dual modulus prescaler (P/P+1), along with the A and B counters, enables the large division ratio, N, to be realised (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the VCO and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17 or 32/33. It is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value and is given by: (P2-P).
fREFIN External reference frequency oscillator.
N = BP + A To PFD
13-BIT B COUNTER
LOAD
From VCO
PRESCALER P/P+1
LOAD
Modulus Control
5-BIT A COUNTER
N DIVIDER
Figure 4. A and B Counters
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REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
R COUNTER
The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N=BP+A) and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The PFD includes a programmable delay element which controls the width of the anti-backlash pulse. This pulse ensures that there is no deadzone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the R Counter Latch, ABP2 and ABP1 control the width of the pulse. See Table 3.
VP
With LDP set to "1", five consecutive cycles of less than 15ns are required to set the lock detect. It will stay set high until a phase error of greater than 25ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10k nominal. When lock has been detected this output will be high with narrow low-going pulses .
DVDD
Analog Lock Detect
Digital Lock Detect R Counter Output N Counter Output MUX
CONTROL
MUXOUT
CHARGE PUMP
SDOUT
HI
D1
U1
Q1
UP
R DIVIDER
CLR1
PROGRAMMABLE DELAY
ABP2 ABP1
U3
CP
DGND
HI
D2
CLR2 DOWN Q2
U2
Figure 6. MUXOUT Circuit
CPGND
N DIVIDER
INPUT SHIFT REGISTER
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2 and M1 in the Function Latch. Table 5 shows the full truth table. Figure 6 shows the MUXOUT section in block diagram form.
Lock Detect
The ADF4360 family's digital section includes a 24-bit input shift register, a 14-bit R counter and a 19-bit N counter, comprising a 5-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two lsb's DB1, DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table 6. Table 1 shows a summary of how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits C2 C1 0 0 1 1 0 1 0 1 Data Latch Control Latch R Counter N Counter (A & B) Test Modes Latch
MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect Digital lock detect is active high. When LDP in the R Counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive Phase Detector cycles is less than 15ns.
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PRELIMINARY TECHNICAL DATA ADF4360
VCO
The VCO core in the ADF4360 family uses eight overlapping bands as shown in figure 7 to allow a wide frequency range to be covered without a large VCO sensitivity (Kv) and resultant poor phase noise and spurious performance. The correct band is chosen automatically by the band select logic at power-up or whenever the N Counter latch is updated. It is important that the correct write sequence be followed at power-up. This sequence is: 1) R Counter latch 2) Control latch 3) N Counter latch During band select, which takes five PFD cycles, The VCO Vtune is disconnected from the output of the loop filter and connected to an internal reference voltage.
After band select, normal PLL action resumes. The nominal value of Kv is 75MHz/Volt (for the ADF4360-1/ 2) or 37.5MHZ/Volt if divide by two operation has been selected (by programming DIVSEL high in the N Counter latch). The ADF4360 family contains linearisation circuitry to minimise any variation of the product of Icp and Kv. The Phase Noise of the VCO is best at high power levels. To allow the user to optimise this noise-power trade off depending on his/her requirements. The operating current in the VCO core is programmable in four steps, 5mA, 10mA, 15mA & 20mA. This is controlled by bits PC1 & PC2 in the Control latch.
OUTPUT STAGE
The RFoutA and RFoutB pins of the ADF4360 family are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO. To allow the user to optimise his/her power dissipation vs output power requirements, The tail current of the differential pair is programmable via bits PL1 & PL2 in the Control latch. Four current levels may be set; 3mA, 4.5mA, 6.5mA and 9.5mA giving output power levels of -3dBm, -6dBm, 9dBm & -12dBm into a 50ohm load. Alternatively, both outputs can be combined in a 1+1:1 transformer or a 180 microstrip coupler. Another feature of the ADF4360 family is provided whereby the supply current to the RF output stage is shut down until the part achieves lock as measured by the Digital Lock detect circuitry. This is enabled by the MTLD (Mute Till Lock Detect) bit in the Control latch.
Figure 7 Band Select vs Vtune
The R Counter output is used as the clock for the band select logic and should not exceed 250 kHz. A programmable divider is provided at the R Counter input to allow division by 1,2,4 or 8, and is controlled by bits BSC1 and BSC2 in the R Counter Latch. Where the required PFD frequency exceeds 250 kHz the divide ratio should be set to allow enough time for correct band selection.
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PRELIMINARY TECHNICAL DATA ADF4360
LATCH STRUCTURE
The diagram below shows the four on-chip latches for the ADF4360 family. The two LSB's decide which latch is programmed.
Control Latch
Mute Till LD Power Down 2 Power Down 1 Counter Reset CP Gain
Phase Detector Polarity
CP 3-State
Prescaler Value
Current Setting 2
Current Setting 1
Output Power Level
MUXOUT Control
DB7 M3 DB6 M2 DB5 M1
Core Power Level
DB3 PC2 DB2 PC1
Control Bits
DB1 DB0
DB23 DB22 DB21 P2 P1 PD2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1
DB11 DB10 DB9 MTLD CPG CP
DB8 PDP
DB4 CR
C2 (0) C1 (0)
N Counter Latch
Reserved
Divide by 2 Select
CP Gain
CPG B13 B12 B11 B10
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DIVSEL DIV2
Reserved
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV6 RSV5 BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9
Divide by 2
13-Bit B Counter
5-Bit A Counter
Control Bits
DB2 A1 DB1 DB0
DB9 B2
DB8 B1
DB7 RSV7
DB6 A5
DB5 A4
DB4 A3
DB3 A2
B9
B8
B7
B6
B5
B4
B3
C2 (1) C1 (0)
R Counter Latch
Test Mode Bit
Lock Detect Precision
Band Select Clock
Anti Backlash Width
14-Bit Reference Counter, R
Control Bits
DB6 R5 DB5 R4 DB4 R3 DB3 R2 DB2 R1 DB1 DB0
DB9 R8
DB8 R7
DB7 R6
C2 (0) C1 (1)
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PRELIMINARY TECHNICAL DATA ADF4360
CONTROLLATCH With (C2, C1) = (0,0), the Control Latch is programmed.
Control Latch
Mute Till LD Power Down 2 Power Down 1 Counter Reset CP Gain
Phase Detector Polarity
CP 3-State
Prescaler Value
Current Setting 2
Current Setting 1
Output Power Level
MUXOUT Control
DB7 M3 DB6 M2 DB5 M1
Core Power Level
DB3 PC2 DB2 PC1
Control Bits
DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP
DB8 PDP
DB4 CR
C2 (0) C1 (0)
Prescaler Value In the ADF4360 family, P2 and P1 in the Control Latch set the prescaler values. P2 0 0 1 1 P1 0 1 0 1 Prescaler Value 8/9 16/17 32/33 32/33
Power Down DB21 (PD2) and DB20 (PD1) provide programmable power-down modes. In the programmed asynchronous power-down, the device powers down immediately after latching a "1" into bit PD1, with the condition that PD2 has been loaded with a "0". In the programmed synchronous power-down, the device power down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a "1" into bit PD1 (on condition that a "1" has also been loaded to PD2), then the device will go into power-down on the second rising edge of the R counter output, after LE goes high. When a power down is activated (either synchronous or asynchronous mode ), the following events occur: All active DC current paths are removed. The R, N and timeout counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital clock detect circuitry is reset. The RFIN input is debiased to a high impedance state. The reference input buffer circuitry is disabled. The input register remains active and capable of loading and latching data. PD2 X 0 1 PD1 0 1 1 Mode Normal Operation Asynchronous Power-Down Synchronous Power-Down
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PRELIMINARY TECHNICAL DATA ADF4360
Control Latch
Mute Till LD Power Down 2 Power Down 1 Counter Reset CP Gain
Phase Detector Polarity
CP 3-State
Prescaler Value
Current Setting 2
Current Setting 1
Output Power Level
MUXOUT Control
DB7 M3 DB6 M2 DB5 M1
Core Power Level
DB3 PC2 DB2 PC1
Control Bits
DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP
DB8 PDP
DB4 CR
C2 (0) C1 (0)
Charge Pump Currents CPI3, CPI2, CPI1 in the ADF4360 family determine Current Setting 1. CPI6, CPI5, CPI4 determine Current Setting 2. The truth table is given below.
CPI6 CPI3 0 0 0 0 1 1 1 1
CPI5 CPI2 0 0 1 1 0 0 1 1
CPI4 CPI1 0 1 0 1 0 1 0 1
ICP 0.31 mA 0.62 mA 0.93 mA 1.25 mA 1.56 mA 1.87 mA 2.18 mA 2.50 mA
Output Power Level The output power level of the VCO is set by these bits
PL2 PL1 0 0 0 1 1 0 1 1
Output Power Level (dBm into 50 ohm) -12 -9 -6 -3
Mute Till Lock Detect DB11 of the Control Latch in the ADF4360 family is the Mute Till Lock Detect Bit. When this is programmed to a "1", the RF output is disabled until digital lock detect goes high. CP Gain Bit DB10 of the Control Latch in the ADF4360 family is the Charge Pump Gain bit. When this is programmed to a "1" then Current Setting 2 is used. When programmed to a "0", Current Setting 1 is used. Charge Pump Three-State This bit puts the charge pump into three-state mode when programmed to a "1". It should be set to "0" for normal operation. Phase Detector Polarity The PDP bit in the ADF4360 family sets the Phase Detector Polarity. When the VCO characteristics are positive this should be set to "1". This is the normal setting when using the on-chip VCO, with a passive loop filter or an active non-inverting filter. It can also be set to "0". This is required if an active inverting loop filter is used.
REV. PrP 01/03
-12-
PRELIMINARY TECHNICAL DATA ADF4360
Control Latch
Mute Till LD Power Down 2 Power Down 1 Counter Reset CP Gain
Phase Detector Polarity
CP 3-State
Prescaler Value
Current Setting 2
Current Setting 1
Output Power Level
MUXOUT Control
DB7 M3 DB6 M2 DB5 M1
Core Power Level
DB3 PC2 DB2 PC1
Control Bits
DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG CP
DB8 PDP
DB4 CR
C2 (0) C1 (0)
MUXOUT Control The on-chip multiplexer is controlled by M3, M2, M1.
M3 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1
MUXOUT Three-State Output Digital Lock Detect N Divider Output DVDD R Divider Output N-Channel Open Drain Lock Detect Serial Data Output DGND
Counter Reset DB4 is the counter reset bit for the ADF4360 family. When this is "1", the R counter and the A,B counters are reset. For normal operation this bit should be "0".
Core Power Level PC1 and PC2 set the power level in the core.
PC2 PC1 0 0 0 1 1 0 1 1
Core Power Level 5mA 10mA 15mA 20mA
-13-
REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
R COUNTER LATCH With (C2, C1) = (0,1), the R CounterLatch is programmed.
R Counter Latch
Test Mode Bit
Lock Detect Precision
Reserved
Band Select Clock
Anti Backlash Width
14-Bit Reference Counter, R
Control Bits
DB6 R5 DB5 R4 DB4 R3 DB3 R2 DB2 R1 DB1 DB0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV6 RSV5 BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
C2 (0) C1 (1)
R Counter R1 to R14 sets the counter divide ratio. The divide range is 1 (00.....001) to 16383 (111......111). Anti-Backlash Pulse Width DB16 and DB17 set the anti-backlash pulse width. ABP2 ABP1 0 0 0 1 1 0 1 1 Anti-Backlash Pulse Width 3.0ns 1.5ns 6.0ns 3.0ns
Lock Detect Precision Bit DB18 is the Lock Detect Precision Bit and sets the number of references cycles for entering the locked state. With LDP at "1", 5 cycles are taken and with LDP at "0", 3 cycles are taken. Test Mode Bit DB19 is the Test Mode Bit (TMB). With TMB = 0, the contents of the Test Mode Latch are ignored and normal operation occurs as determined by the contents of the Control Latch, R Counter Latch and N Counter Latch. External Band Select = 0, Band Control of ICP = 1, and SAR control of ICP = 1. This is normal operation. With TMB = 1, the contents of the Test Mode Latch are enabled and will control the mode of operation. These are defined in the Test Modes Latch. Band Select Clock Bits These Bits set a divider for the band select logic clock input, The output of the R Counter is by default the value used to clock the band select logic, but if this value is too high (>250kHz), a divider can be switched in to divide the R counter output to a smaller value. BSC2 BSC1 0 0 0 1 1 0 1 1 Band Select Clock Divider Value 1 2 4 8
Reserved Bits DB23 - DB22 are spare bits and have been designated as "Reserved".
-14-
REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
A,B COUNTER LATCH With (C2, C1) = (1,0), the A, B Counters Latch is programmed.
N Counter Latch
Reserved
Divide by 2 Select
CP Gain
CPG B13 B12 B11 B10
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DIVSEL DIV2
A Counter Latch A5 - A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111). B Counter Latch B13 - B1 program the B counter. The divide range here is 3 (00.....0011) to 8191 (11....111). Overall Divide Range The overall divide range is defined by ((PxB) + A), where P is the prescaler value. CP Gain Bit DB21 of the N Counter Latch in the ADF4360 family is the Charge Pump Gain bit. When this is programmed to a "1" then Current Setting 2 is used. When programmed to a "0", Current Setting 1 is used. This bit can also be programmed via DB10 of the Control Latch. The bit will always reflect the latest value written to it, whether this is through the Control Latch or the N Counter Latch. Divide by 2 DB22 is the divide-by-2 bit. When set to a "1", the output divide by 2 function is chosen. When it is set to "0", normal operation occurs. Divide by 2 Select DB23 is the divide-by-2 select bit. When this is programmed to a "1", the divide-by-2 output is selected as the prescaler input. When it is set to a "0", the fundamental is used as the prescaler input.
Divide by 2
13-Bit B Counter
5-Bit A Counter
Control Bits
DB2 A1 DB1 DB0
DB9 B2
DB8 B1
DB7 RSV7
DB6 A5
DB5 A4
DB4 A3
DB3 A2
B9
B8
B7
B6
B5
B4
B3
C2 (1) C1 (0)
-15-
REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
POWER UP CONDITIONS On power-up, Reset Bit stays low and CPI 3-State stays high until a valid Control write, R write and N write have been completed. The device comes up in power-down mode and stays in this mode until the valid writes have been completed. PUTTING THE CHARGE PUMPINTO 3-STATE Three conditions can potentially three-state the charge pump. a) The initialisation sequences (reset counters cp -> tri-state). b) The CP 3-State bit in the function latch Note that a) takes priority over b). That is to say: * If CP is tri-state due to an initialialisation sequence then the function latch CP 3-state bit is `dont care'.
-16-
REV. PrP 01/03
PRELIMINARY TECHNICAL DATA ADF4360
OUTLINE DIMENSIONS Dimensions shown in inches and (mm)
0.157 (4.0) BSC SQ PIN 1 INDICATOR
0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 19 0.009 (0.24) 18 0.148 (3.75) BSC SQ 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30)
0.010 (0.25) MIN
BOTTOM VIEW 24 1
TOP VIEW
0.080 (2.25) 0.083 (2.10) SQ 0.077 (1.95)
13 12 6 7
12 MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE 0.020 (0.50) BSC
o
0.028 (0.70) MAX 0.026 (0.65) NOM
0.098 (2.50) REF
0.008 (0.20) REF
0.002 (0.05) 0.0004 (0.01) 0.0 (0.0)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
-17-
REV. PrP 01/03

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